Crystal controlled movement with frequency dividing circuitry

ABSTRACT

Timekeeping apparatus in which a precision crystal oscillator is used as a frequency reference, the output of which is divided in frequency by a multi-stage binary divider before being converted to effect mechanical movement of a time display, the reference frequency and number of divider stages being chosen to produce a low divider output frequency to allow the display to be advanced with inexpensive mechanical parts. The intermediate stages of the divider chain are tapped to produce output signals for driving an alarm speaker associated with the primary time display.

United States Patent [191 Preiser 1 CRYSTAL CONTROLLED MOVEMENT WITHFREQUENCY DIVIDING CIRCUITRY [75] Inventor: Ralph H. Preiser, La Salle,Ill.

[73] Assignee: General Time Corporation, Phoenix,

Ariz.

[22] Filed: Jan. 22, 1970 [21] Appl. No.: 4,865

[52] US. Cl. ..58/38, 58/19 R [51] Int. Cl ..G04c 21/12, G04c 21/16 [58]Field of Search ..58/l9, 23, 33, 38

[56] References Cited UNITED STATES PATENTS 3,212,252 10/1965 Nakai..58/23 3,485,033 12/1969 Langley, ..58/50 3,505,804 4/1970 Hofstein..58/23 BA FOREIGN PATENTS OR APPLICATIONS 1,177,523 11/1970 GreatBritain ..58/23 A 1,517,115 2/1968 France"; ..58/23 A PrimaryExaminer-Stephen J. Tomsky Assistant ExaminerEdith C. Simmons JackmonAttorney-Rennie, Edmonds, Morton, Taylor & Adams ABSTRACT Timekeepingapparatus in which a precision crystal oscillator is used as a frequencyreference, the output of which is divided in frequency by a multi-stagebinary divider before being converted to effect mechanical movement of atime display, the reference frequency and number of divider stages beingchosen to produce a low divider output frequency to allow the display tobe advanced with inexpensive mechanical parts. The intermediate stagesof the divider chain are tapped to produce output signals for driving analarm speaker associated with the primary time display.

9 Claims, 6 Drawing Figures Patented April 24, 1973 INVENTOR 37 RALPH H.PREISER 3 Sheets-Sheet l CRYSTAL CONTROLLED MOVEMENT WITH FREQUENCYDIVIDING CIRCUITRY Clocks and watches produced for the consumer marketare subject to a number of constraints in their design and manufacture.They must provide accuracy over long periods of time, require a minimumnumber of parts, be easily assembled, and be inherently inexpensive. D-Coperated clocks and watches additionally require that the powerconsumption be very low to avoid the expense and inconvenience ofcharging or replacement of batteries. Electronic watches in particularimpose a severe space restriction while requiring a high degree ofaccuracy and lowest possible battery drain.

Accuracy in an electric clock is primarily dependent upon the accuracyand stability of the oscillator which is employed as a frequency base.However, oscillators running at low clock frequencies, such as one cycleper second, are inherently large, relatively inaccurate and expensive.One known technique for overcoming this problem involves using anelectro-mechanical oscillator operating in the 200-500 l-Iz. frequencyrange with speed reduction gearing to divide down to clock hand speed.But it has been found difficult to convert electronic oscillations intorotary motion at such high oscillator frequencies.

It is the main object of the invention to satisfy numerous designrestraints such as those noted above and to overcome the drawbacks andinadequacies of previous clock and watch drives incident to producing anelectrical drive signal at a low frequency to achieve economy in thechoice of mechanical parts and reducing the speeds at which such partsmust move to optimize overall performance.

It is a general object of the present invention to provide a precisionelectronic timepiece having a high degree of accuracy and stability, onthe order of a few parts per million, over long periods of time and overnormally encountered temperature variations.

It is another object of the present invention to provide a drive for anelectric timepiece which may be powered by a small storage battery,about the size of a small coin, and which is inherently compact for useuniversally in watches.

A further object of the present invention is the provision of electronictimekeeping apparatus providing an accurate and stable time displaywhile at the same time providing a plurality of synchronized signals ataudio frequency for application to peripheral apparatus, especially atime triggered alarm.

Other objects and advantages of the present invention will becomeevident upon reading the attached detailed description and uponreference to the drawings in which:

FIG. 1 is a perspective view, simplified and partially diagrammatic, ofan alarm clock mechanism for use in the present invention;

FIG. la shows a friction" forming a part of the mechanism of FIG. 1;

FIG. 2 is a horizontal section taken through the mechanism of FIG. 1;

FIG. 3 is a schematic diagram, partially in block form, of the circuitryused in the oscillator, shaper and divider portions of the circuit;

FIG. 4 is a schematic diagram of the auxiliary circuitry used in thealarm version of the present invention; and

FIG. 5 shows application of the invention to the driving of a timingtrain in a watch.

While the invention has been described in connection with the preferredembodiment, it will be understood that I do not intend to be limited tothe particular embodiments set forth, but intend, on the contrary, tocover the various alternatives, modifications and equivalents as may beincluded within the spirit and scope of the invention.

Turning now to the drawings, there is shown in FIGS. 1 and 2 an alarmclock mechanism 20 which may be used in practicing the invention andhaving a face 21. The first gear in the timing train is a seconds wheel3 which is driven, by means to be described, at the average rate of l r.p. m. The seconds wheel 30 has a shaft 31, at the forward end of whichis mounted a seconds hand 32. The seconds wheel also has a pinion 33which meshes with a step-down gear 34 having a pinion 35. The pinion isrotatable with respect to the gear and is drivingly coupled to it bymeans of a friction, illustrated in FIG. 1a, which includes a star wheel36, which is directly coupled to the pinion 35, a

and pawls 37, three in number, and each of which is anchored to the gearat 38 so as to bias the tip 39 resiliently inward into engagement withthe star wheel. The result is a detent or click type of friction whichprovides sufficient torque for normal driving but which may be readilyoverpowered during manual setting of the hands.

Meshing with the pinion 35 is a minute wheel 40 connected to a shaft 41having a minute hand 42. A further l2:l reduction is brought about by apinion 43 on the minute wheel meshing with a step down gear 44 having apinion 45 driving an hour wheel 50. The latter has a forwardlyprojecting shaft 51 which amounts the hour hand 52.

For the purpose of triggering the alarm, the hour wheel 50 is slidableaxially and has cams 53 formed on the face thereof. Arranged adjacentthe hour wheel is an alarm set wheel 60 having a hollow shaft 61 andhand 62 and carrying a corresponding set of cams 63 opposed to the cams53. When the cams 53, 63 ridge up .upon one another at a pre-set alarmtime, the inward axial movement of the hour wheel 50 serves to triggeran alarm (to be described'shortly) by closing a pair of switches 70, 71in the alarm circuitry. A manual alarm control knob 72 is provided,which, when pushed forward, disables the alarm circuitry via amechanical connection to a pair of switches 73, 74 respectively inseries with the switches 70, 71. To change the phase position of thealarm set wheel 60, a setting shaft 65 is provided having a spade lug 66thereon which, when the shaft 65 is pushed inwardly, engages a slot 67formed in an alarm set pinion 68 (see FIG. 2). The alarm set pinionrotates the alarm set wheel 60 which repositions the cams 63 and thealarm set hand 62.

For setting the indicated time, the pinion 35 on the reduction gear 34is provided with a slot 69 which may be engaged by the lug 66 when theshaft 65 is pulled outwardly prior to rotation. Idle clicking occurs atthe star wheel 36 so that the gear train leading to the motor remainsstationary during setting of the time.

In accordance with the present invention, a crystal controlledoscillator is provided operating at a relatively high super audiofrequency on the order of 262, 144 Hz. Also provided are divider stagesin the form of flipflop devices for dividing the oscillator signal downto a frequency on the order of 1 Hz. and suitable for pulsing a steppingmotor or the like for driving of a slow speed wheel in a clock train,with a signal at an audio frequency being tapped from one of theintervening divider stages to be connected to a transducer for soundingthe alarm at the pre-set time.

Referring to FIG. 3, there is shown a highly precise and stable pulsesource including a crystal oscillator 75 and a pulse shaper 76. Thecrystal oscillator shown in FIG. 3 is only intended to be illustrativeof the high frequency oscillators which may be used to produce thereference pulses and is not claimed to be inventive per so. It includesa single stage comprised of an NPN transistor 78 biased by a pair ofbase resistors '79, 80 respectively connected to a positive voltagesupply terminal 81 and ground 82. The emitter of the transistor 78 isconnected to ground through an emitter resistor 84 shunted by acapacitor 85. A dropping resistor 87 connects the collector of thetransistor 78 to the positive supply. A form of inductance-capacitancetuning is provided by a resonance circuit 88 connected to the collectorof the transistor 78. The resonance circuit includes the quartz crystalC in parallel with a voltage divider consisting of a pair of capacitors89, 90, the junction between the capacitors being grounded via a line91. The necessary regenerative feedback is provided by a connectionbetween the resonance circuit 88 and the base of the transistor 78.

In operation, the single stage, acting as a commonemitter amplifier,drives the resonance circuit 88 utilizing the parallel resonance mode ofthe crystal C. The voltage developed across the capacitor 90 is 180degrees out of phase with the voltage at the collector of the transistor78. This out of phase voltage is applied as a feedback signal betweenthe base of the transistor 78 and ground for sustaining oscillation. Theoscillating frequency of this circuit is determined by the resonantfrequency of the crystal C and the value of the capacitors 89, 90 andpreferably is on the order of 262,144 I-Iz. A more thorough explanationof the operational characteristics of this crystal oscillator can befound in US. Army Technical Manual No. ill-690 Basic Theory andApplication of Transistors. A coupling capacitor 94 is provided to blockthe D-C. component of the amplified signal at the collector of thetransistor 78 from the output of the oscillator.

For converting the output of the crystal oscillator, which issinusoidal, into a series of pulses having sharply defined rising andtrailing edges, a pulse shaper 76 is provided which includes a pair oftransistors 100, 101. A ground reference resistor 102 insures that theoutput of the oscillator 75 swings symmetrically above and below ground,and an input resistor 103 applies this signal to the transistor 100. Theemitter of the transistor 100 is grounded so that the transistorconducts only during the positive half cycles of the oscillator outputsignal. The amplified signal is fed from the collector of the transistor100 to the base of the transistor 101 through a coupling resistor 105,while a bias resistor 106 connects the base to the positive supplyterminal 81 to insure that the transistor 101 is not rendered conductiveby collector-to-base leakage current. A dropping resistor 108 referencesthe collector of the transistor 101 to ground when the transistor is notconducting. In operation, the positive half cycle from the crystaloscillator renders the transistor conductive, drawing a greatlyamplified current through the resistor and the base-emitter junction ofthe transistor 101, which current in turn is amplified in thecollector-emitter circuit of the transistor 101 to cause a step rise inthe voltage across the resistor 108. A negative half cycle at theoscillator output quickly pulls the first transistor 100 out ofconduction, depriving the transistor 101 of base current and renderingit non-conductive. The result is an abrupt decrease in the voltageacross the resistor 108. The resulting signal at the shaper output is asharply defined square wave having the same frequency and phase as theoutput from the crystal oscillator 75.

Crystal-controlled oscillators characteristically have an extremely highQ (narrow band width) and good frequency stability over a giventemperature range. In carrying out the present invention a crystalfrequency is chosen in excess of 8 k Hz. and preferably above 100 k Hz.and less than 300 k Hz., with tandem divider stages being utilized todivide the frequency down to a low frequency on the order of 1 Hz. Whileit has been found that crystals having resonant frequencies as low as 8k I-Iz. will provide the necessary stability when the present inventionis used in a clock, it is preferred, for both clocks and watches, to usea crystal frequency of 262,144 Hz. with division by 2 to produce the 1Hz. output signal. To this end, the embodiment of FIG. 3 includes aseries of binary division elements FFl-FF18 which can typically take theform of conventional divide-by-two flip-flops. Each of these flip-flopsreceives an input signal at a clock, or toggle, terminal T and producesoutput signals at a pair of output terminals Q, 5 which are mutuallyopposite in phase and at one half the frequency of the input signal. TheQ output terminal of each flip-flip is connected to the toggle terminalT of the succeeding flip-flop so that, assuming a reference pulsefrequency of 262,144 112., the eighteen stages of the divider willrespectively have outputs at 131,072 65,536 32,768 16,384 8,192 4,0962,048- 1,024-512-256- l28-6432- 16-8-4- 2 and 1 Hz.

For the purpose of utilizing the 1 Hz. square output wave from the finaldivider stage an amplifier and single stepping type, or ratchet, motorare used, coupled to the seconds wheel 30 of the clock train shown inFIGS. 1 and 2. The amplifier indicated at is a high gain NPN stagehaving an input resistor 116. The motor is in the form of anelectromagnet, preferably a solenoid, having a coil 118 and an armature119 carrying a pawl 120 which acts upon ratchet teeth 121 formed on theperiphery of the seconds wheel 30. The ratchet teeth are 60 in number sothat the seconds hand 32 is advanced one division on the clock dial foreach impulse. A return spring 122 returns the pawl 120 after each powerstroke. A keeper pawl 123 prevents retrograde movement.

For illustrating the circuit, the first binary divider stage F F-l isset forth in schematic form to show a typical dividing flip-flop. Thiscircuit includes a pair of NPN transistor stages 130, 131 with theiremitters tied to a common ground tenninal 132. The circuitry associatedwith each of these transistors 130, 131 forms a symmetric configuration.A pair of collector resistors 134, 135 form the respective loads for thetransistors 130, 131. The collector of transistor 13% is coupled to thebase of the transistor 131 through a resistor 136 which is shunted by anaccelerating capacitor 137. Similarly, the collector of the transistor131 is connected to the bae of the transistor 136 through a resistor 138and an accelerating capacitor 139.

One skilled in the art will readily appreciate that, in the stablestate, one of the transistors 130 or 131 will be saturated while theother transistor is cut-off. Thus, there are two possible stable states,depending upon which transistor is conducting. For switching the circuitfrom one stable state to the other, there is provided a steering networkincluding an input path to the base of the transistor 13h which includesan input resistance 142, a differentiating capacitor 143 and a diode 144connected in series. Similarly, an input path to the base of thetransistor 131 includes an input resistor 146, a differentiatingcapacitor 147 and a diode 148. The input paths are tied together at thetoggle terminal T of the flip-flop FF-l. A blocking diode 15% connectsthe collector of transistor 13% to the connection between the inputresistor 142 and the differentiating capacitor 143 to prevent a positiveinput pulse applied at the toggle terminal T from reaching the base ofthe transistor 13% when that transistor is already conducting.Similarly, a blocking diode 1.51 connects the collector of thetransistor 131 to the junction between the input resistor 146 and thedifferentiating capacitor 147 to block an input pulse from the base ofthe transistor 131 when that transistor is conducting.

To understand the operation of this circuit, first assume that thetransistor 13% is conducting and saturated while transistor 131 is atcut-off. A positive pulse applied at the toggle terminal T causescurrent to pass through both input resistors 142 and 146. However, thecurrent through resistor 142 is shunted to ground through the diode 15dand the saturated collectoremitter junction of the transistor 130. Sincethe transistor 131 is originally at cut-off, the voltage at itscollector, and at the cathode of diode 151, is high, and the input pulseapplied through the resistor M6 passes freely to be differentiated bythe capacitor 147 and applied to the base of the transistor 131 throughthe diode 148, rendering the transistor 131 conductive. As the voltageat the collector of the transistor 131 falls, a corresponding voltagedecrease is applied to the base of the transistor 130 through thepreviously charged accelerating capacitor 139, sharply turning off thetransistor 130. As a result, the collector voltage of the transistor13f) rises sharply and is applied to the base of v transistor 131 asregenerative feedback through the capacitor 137 and coupling resistor136. Thus, an abrupt change of state has taken place and the output Q isnow effectively at ground voltage. The negative half cycle of the pulseat the toggle terminal T has no effect on the circuit because of thepolarity of the diodes 144, 148, 150 and 151. The next positive inputpulse is blocked from the now-conducting transistor 131 by the diode 151while being differentiated by the capacitor 143 to apply a current spiketo the base of the transistor 130. The whole process begins over againin the opposite direction from that described previously. The chargedcapacitor 137 couples the decreasing collector voltage from thetransistor 130 to turn off the transistor 131, which, in tum, applies anincreasing voltage from the collector of the transistor 131 to the baseof the transistor in a regenerative fashion. Th e circuit abruptlychanges states to render the output Q low in voltage and the output Qhigh in voltage. Thus, it is seen that a positive pulse results at theoutput terminal Q with every second positive pulse at the toggleterminal T, producing division by two.

In carrying out the present invention, an alarm device is provided inthe form of a small transducer, or speaker, energized at the pre-settime by an audio signal from one of the intermediate stages of thebinary divider. More specifically, audio signals are taken from two ofthe divider stages and combined in such a way as to produce a pleasingwake-up sound. To this end, the embodiment shown in FIG. 4 includes analarm circuit 1'70, with the crystal oscillator 75 and pulse shaper 76being shown in block form, and the series of divide-bytwo flip-flopsFFll-Ffifi being represented by the binary divider 171. In thisinstance, two audio outputs 1'72, 173 are taken from divider stages FPSand FF9 respectively, the selected frequencies being preferably 1024 Hz.and 512 Hz, in addition to the regular l Hz. output 17%. An outputspeaker 177 has a drive coil 178 forming the load for a single stagetransistor amplifier 179. The amplifier 1'79 inciudes a PNP transistor180 having its emitter lead connected to the positive supply terminal181. A bias resistor 182 and an input resistor 183 are connected to thebase of the transistor 180.- Any of the audio frequency signals producedby the binary divider may be applied to the amplifier 179 to drive thespeaker 177, however, of the frequencies present in this dividerarrangement, the 512 and 1024 Hz. signals have been found to produce amost pleasing effect. For control of the alarm means by the clockmechanism there is provided a mechanical switch 185 having a firstcontact arm 11% inserted in series with the input resistor 183 to thetransistor 180 and which is coupled to the hour wheel 50 (PEG. 1) bymeans of a mechanical connection 187 to make contact at the presetwake-up time.

Further in accordance with the teachings of the present invention, Iprovide a commutating means for alternately connecting the selectedaudio frequency signals from the frequency divider to the alarm speaker177. To this end, the alarm circuit 170 of FIG. 4 includes a commutatingrelay 1%) having an energization coil 191, a normally open contact 192and a normally closed contact 193. The contacts 192, 193 arerespectively inserted in series with the 512 Hz. output 173 and the 1024Hz. output 172 of the binary divider 171. The energization coil 191 ispulsed intermittently by a transistor 195 responding to a signal appliedthereto. The emitter of the transistor 195 is connected to ground whilethe collector is connected to the positive supply terminal 181 throughthe coil 191. An input resistor 196 connects the base of the transistor195 to an input line 197. Any one of a number of different commutatingfrequencies are available from the binary divider 171. In this instance,the input line 197 to the commutating circuit is driven from the 1 Hz.divider output 174. A second contact arm 188 of the mechanical switch185 controls the application of the 1 Hz. signal to the commutator inputline 197 and insures that the commutator circuit draws power from thesupply terminal 181 only when the alarm mechanism of the time display isactuated.

When the set time is reached for sounding the alarm, the mechanicalconnection 187 closes the contact arms 186, 188 of the switch 185. Thepositive-going pulse from the l Hz. divider output 174 renders thetransistor 195 conductive to energize the relay 190, causing the contact192 to close and contact 193 to open. A burst of pulses at 512 Hz. willbe fed through the now-closed circuit to the alarm amplifier 179,energizing coil 178 and speaker 177 at l2 Hz. One-half second later the1 Hz. output 174 falls to 0 volts and the transistor 195 is renderednon-conductive. As the relay 190 is de-energized, the contact 192 openswhile the contact 193 closes. The 1024 Hz. output 172 is connected todrive the alarm amplifier 179 and to thereby excite the speaker coil 178and the speaker 177 at 1024 Hz. The commutating action will continueuntil the alarm is shut off, which may be accomplished by the alarmcontrol knob 72 coupled to switches 73 and 74 in the manner shown inFIG. 1 and 4.

Another feature of the embodiment shown in FIG. 4 is the provision of athree-position switch 205 for selectively applying either a steady 512Hz. signal, a steady 1024 Hz. signal or the aforementioned commutatedsignal to the alarm amplifier 179 when the alarm goes off. With thisprovision the user manually dial his preferred alarm sound.

Since the divider output signals are all in the form of square-wavepulse trains, the signal applied to the speaker 177 will not produce apure single-frequency tone. A square wave includes many harmonics of thefundamental frequency, and a certain amount of higher frequencycomponents will exist in the output sound from the speaker 177 inaddition to the fundamental 512 or 1024 Hz. signal. It has been foundthat this does not make the sound any less pleasing, but, on thecontrary, it seems to add a fullness pleasing to the ears of mostlisteners. However, if it is desired to eliminate the higher frequencycomponents from the speaker signals, a band pass filter may be insertedsomewhere between the binary divider outputs and the speaker coil 178.

One of the primary advantages of utilizing frequency division circuitryin the present invention lies in the adaptability of such circuitry tofabrication in an integrated circuit. In a practiced form of theinvention, the crystal oscillator 75, the pulse shaper 76 and the binarydivider 171 are all incorporated into a single integrated circuit havingoutput terminals for connecting to ground, a D-C. power source, theclock train drive mechanism, and a suitable reference crystal. One ofthe benefits of integrating the electrical circuitry is illustrated inFIG. 5, which shows the primary elements of the present inventionembodied in a wristwatch. In this form, the electronic time piececonsists of a watch housing 210 having a face 211 which is partially cutaway to reveal the internal parts arrangement. The electronics portionof the present invention is fabricated into a single integrated circuit214. D-C. power for the integrated circuit is applied by two smallstorage batteries 216, 217 connected in series and adapted to supply thecircuit via a ground line 218 and a 8+ line 219. The frequency referenceis provided by a crystal 222 connected to the integrated circuit via apair of connecting lines 223, 224. The 1 Hz output from the dividersection of the integrated circuit is,

brought out on a terminal 228 and connected to energize a stepping motorindicated generally at 230. For purposes of illustration, the steppingmotor 230 set forth here is in the form of a ratchet wheel-escapementmechanism comprised of a pallet 231 having a pair of pallet pins 232adapted to cooperate with a series of cam-teeth 234 of a seconds drivewheel 235. The pallet 231 is pivotable in oscillatory fashion about apivot pin 237 and is adapted to be controlled through a L-shaped leverarm 238 which cooperates with a stepping solenoid 239. The steppingsolenoid 239 is grounded at one end while having its other end connectedfor energization by the 1 Hz. output 228 of the integrated circuit. Thelever arm 238 is biased against the force of the solenoid 239 by areturn spring 240. The ratchet wheel 235 will preferably have cam-teethequally spaced around its periphery so as to properly advance a secondshand 236 to which it is attached.

As the voltage at the 1 Hz. output terminal 228 of the integratedcircuit 214 rises, the solenoid 239 will become energized to advance theseconds hand 236 over a one-half second increment via the camming actionof the lower pallet pin 232 on one of the ratchet teeth 234. When the 1Hz. output 228 falls to a low voltage, the pallet 231 will rotateclockwise under the force of the return spring 240 to advance theseconds hand 236 over another one-half second increment by way of thecamming action of the upper pallet pin 232 on another one of the ratchetteeth 234. Therefore, it is seen that the seconds hand 236 is directlyadvanced by the stepping motor 238, an arrangement which eliminates theneed for reduction gearing.

The embodiments of FIGS. 1-3 show only a few of the many possiblevariations of the present invention. The multiplicity of output signalsat different frequencies which are available from the binary divider 171may be used for driving a number of auxiliary devices which are housedin the same environment as the time display. For instance, if the timedisplay is in the form of an automobile clock, a number of intermediatefrequency signals can be tapped from the binary divider 171 to providereference frequencies for such devices as the turn signals, flashersignals, a speed governor and the automobile horn.

Also within the scope of the present invention is the provision of twoor more frequencies from the binary divider 171 to provide a number ofdifferent time references for the same time display. For instance, theaddition of six more flip-flop stages to the embodiment shown in FIGS.'1and 2 would provide a signal suitable for driving the minutes hand of atime display with a minimum of speed conversion gearing. It has proveneconomical in many consumer products to use a small motor to drive thetime display of a clock, and the divider circuitry of the presentinvention could provide an alternating drive for such a motor.

It is further within the scope of this invention to use a frequencydivider employing interstage feedback so as to achieve non-binarydivision. One skilled in the art will recognize that any possibleinteger division factor may be obtained from such a divider. Thestraight binary division is shown only because it is the most economicalto fabricate on a semiconductor chip.

A reference crystal having a resonant frequency on the order of 266,144Hz will provide optimum performance with acceptable power drain in mostapplications. However, when the cost of the binary divider is a factor,it will be advantageous to use a much lower frequency, on the order of8,192 Hz, as the reference frequency. With this lower referencefrequency, a 13 stage binary divider can be used to provide a 1 Hz clockdrive as well as suitable audio frequencies such as 512 and 1024 Hz, fordriving an alarm as in the embodiment of FIG. 3.

A further variation of the present invention is illustrated at thebottom of FIG. 3, where an alternative display drive takeoff 250 isshown as taken from FF 12. The 64 Hz signal available at that point isused to drive a conventional clock drive mechanism illustrated by asynchronous motor 251 coupled to drive a clock train 252. As a practicedexample, the motor can be a pole-pair synchronous motor producing amechanical output at 256 RPM. With speed reduction gearing in the clocktrain such an arrangement can result in a very high precision movementat the lowest possible cost.

I claim as my invention:

1. An electronic timepiece comprising;

a crystal oscillator for producing pulses at a predetermined superaudible reference frequency,

means including a series of frequency divider stages connected to theoscillator and responsive to said pulses having terminals for producinga drive signal at a sub-audible frequency and an alarm signal at anaudible frequency,

time display means including a stepping motor and an electro-mechanicaltransducer, the stepping motor being coupled to the drive signalterminal and the transducer being coupled to the alarm signal terminal,

said time display means having an alarm switch and means for triggeringthe same at a pre-set time, the switch being effectively interposedbetween the alarm terminal and the transducer so that an audible alarmis produced at the pre-set time.

2. An electronic timepiece according to claim 1 wherein said timedisplay means includes time indicating elements advanced by saidstepping motor and wherein said sub audible drive signal is at afrequency corresponding to a standard unit of time, said signal beingdirectly coupled to advance an indicating element of said time displaymeans representing said standard unit of time.

3. An electronic timepiece according to claim 2 wherein said drivesignal has a frequency of 1 Hz and wherein said directly advancedindicating element is a seconds hand.

4. An electronic timepiece according to claim 1 wherein said crystaloscillator produces pulses at a super-audible reference frequency whichis an exact binary multiple of 1 Hz.

5. An electronic timepiece according to claim 1 wherein said referencefrequency is at least a binary magnitude above the audio frequency rangeand wherein said frequency divider stages comprise divideby-twoflip-flops connected in a series chain, each of said flip-flops having apair of mutually complimentary outputs delivering signals at one halfthe frequency of the previous flip-flop output.

6, Timekeeping app ratus com rising; display means inc u ing a step ingmotor and indicator elements for providing a visual time indication,

alarm means operatively associated with said display means and includinga signal amplifier and a speaker,

a precision pulse source producing pulses at a superaudible referencefrequency which is an exact binary multiple of a unit of time,

a binary division unit responsive to said pulses and operative to dividesaid reference frequency by a plurality of binary factors for providinga signal at a sub-audible frequency for driving said display means andat least one signal at an audible frequency for driving said alarmmeans.

7. Timekeeping apparatus according to claim 6 further includingcommutating means controlling the application of at least two of saidaudible frequency signals to said alarm means and controlled by one ofsaid signals at a sub-audible frequency, said sub-audible signaleffecting connection of said audible range signals in alternatingsequence to drive said speaker when said alarm means is actuated.

8. An electronic timepiece comprising in combination a precision sourceof pulses including a crystal oscillator operating at a referencefrequency of at least 8kHZ,

frequency division means mounted on a semiconductor chip and beingresponsive to said pulses for providing a plurality of available outputsignals at frequencies which are sub-multiples of said referencefrequency, including a 641-12 display drive signal, said means includinga plurality of binary divider circuits connected in series,

a multi-pole synchronous motor responsive to said display drive signal,and

time display means driven by said motor and operative to advance at arate proportional to said reference frequency.

9. An electronic timepiece comprising in combination,

a precision source of pulses including a crystal oscillator operating ata reference frequency of at least 8 kHz,

frequency division means mounted on a semi-conductor chip and beingresponsive to said pulses for providing a plurality of available outputsignals at frequencies which are sub-multiples of said referencefrequency, said reference frequency being an exact binary multiple of 1cycle per second, and said means including a plurality of binary dividercircuits connected in series,

time display means responsive to at least one of said available outputsignals and operative to advance at a rate proportional to saidreference frequency, and

an alarm means including a speaker and an amplifier, said divided outputsignals including at least one audio signal coupled to said amplifierfor driving said speaker at a predetermined alarm time.

1. An electronic timepiece comprising; a crystal oscillator forproducing pulses at a predetermined super audible reference frequency,means including a series of frequency divider stages connected to theoscillator and responsive to said pulses having terminals for producinga drive signal at a sub-audible frequency and an alarm signal at anaudible frequency, time display means including a stepping motor and anelectromechanical transducer, the stepping motor being coupled to thedrive signal terminal and the transducer being coupled to the alarmsignal terminal, said time display means having an alarm switch andmeans for triggering the same at a pre-set time, the switch beingeffectively interposed between the alarm terminal and the transducer sothat an audible alarm is produced at the pre-set time.
 2. An electronictimepiece according to claim 1 wherein said time display means includestime indicating elements advanced by said stepping motor and whereinsaid sub-audible drive signal is at a frequency corresponding to astandard unit of time, said signal being directly coupled to advance anindicating element of said time display means representing said standardunit of time.
 3. An electronic timepiece according to claim 2 whereinsaid drive signal has a frequency of 1 Hz. and wherein said directlyadvanced indicating element is a seconds hand.
 4. An electronictimepiece according to claim 1 wherein said crystal oscillator producespulses at a super-audible reference frequency which is an exact binarymultiple of 1 Hz.
 5. An electronic timepiece according to claim 1wherein said reference frequency is at least a binary magnitude abovethe audio frequEncy range and wherein said frequency divider stagescomprise divide-by-two flip-flops connected in a series chain, each ofsaid flip-flops having a pair of mutually complimentary outputsdelivering signals at one half the frequency of the previous flip-flopoutput.
 6. Timekeeping apparatus comprising; display means including astepping motor and indicator elements for providing a visual timeindication, alarm means operatively associated with said display meansand including a signal amplifier and a speaker, a precision pulse sourceproducing pulses at a super-audible reference frequency which is anexact binary multiple of a unit of time, a binary division unitresponsive to said pulses and operative to divide said referencefrequency by a plurality of binary factors for providing a signal at asub-audible frequency for driving said display means and at least onesignal at an audible frequency for driving said alarm means. 7.Timekeeping apparatus according to claim 6 further including commutatingmeans controlling the application of at least two of said audiblefrequency signals to said alarm means and controlled by one of saidsignals at a sub-audible frequency, said sub-audible signal effectingconnection of said audible range signals in alternating sequence todrive said speaker when said alarm means is actuated.
 8. An electronictimepiece comprising in combination a precision source of pulsesincluding a crystal oscillator operating at a reference frequency of atleast 8kHZ, frequency division means mounted on a semiconductor chip andbeing responsive to said pulses for providing a plurality of availableoutput signals at frequencies which are sub-multiples of said referencefrequency, including a 64Hz display drive signal, said means including aplurality of binary divider circuits connected in series, a multi-polesynchronous motor responsive to said display drive signal, and timedisplay means driven by said motor and operative to advance at a rateproportional to said reference frequency.
 9. An electronic timepiececomprising in combination, a precision source of pulses including acrystal oscillator operating at a reference frequency of at least 8 kHz,frequency division means mounted on a semi-conductor chip and beingresponsive to said pulses for providing a plurality of available outputsignals at frequencies which are sub-multiples of said referencefrequency, said reference frequency being an exact binary multiple of 1cycle per second, and said means including a plurality of binary dividercircuits connected in series, time display means responsive to at leastone of said available output signals and operative to advance at a rateproportional to said reference frequency, and an alarm means including aspeaker and an amplifier, said divided output signals including at leastone audio signal coupled to said amplifier for driving said speaker at apredetermined alarm time.